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| A4940 Automotive Full Bridge MOSFET Driver Features and Benefits High current gate drive for N-channel MOSFET full bridge Independent control of each MOSFET Charge pump for low supply voltage operation Cross-conduction protection with adjustable dead time 5.5 to 50 V supply voltage range Diagnostics output Low current sleep mode Description The A4940 is a full-bridge controller for use with external N-channel power MOSFETs and is specifically designed for automotive applications with high-power inductive loads such as brush DC motors. A unique charge pump regulator provides full ( >10 V ) gate drive for battery voltages down to 7 V and allows the A4940 to operate with a reduced gate drive, down to 5.5 V. A bootstrap capacitor is used to provide the above battery supply voltage required for N-channel MOSFETs. A unique bootstrap charge management system ensures that the bootstrap capacitor is always sufficiently charged to supply the high-side gate drive circuit. Each of the power MOSFETs is controlled independently but all are protected from shoot-through by dead time that is userconfigured by an external resistor. Integrated diagnostics provide indication of undervoltage and overtemperature faults. The A4940 is supplied in a 24-pin TSSOP power package with an exposed pad for enhanced thermal dissipation (package type LP). It is lead (Pb) free, with 100% matte tin leadframe plating (suffix -T). Package: 24-pin TSSOP with exposed thermal pad (suffix LP) Not to scale Typical Application FAULT VBAT AHI BHI A4940 M ALO BLO A4940-DS A4940 Automotive Full Bridge MOSFET Driver Selection Guide Part Number A4940KLPTR-T Packing 4000 pieces per reel Absolute Maximum Ratings* Characteristic Load Supply Voltage Logic Supply Voltage Logic Inputs Logic Outputs Pin VREG Pins CP1, CP2 Pin RDEAD Pins SA, SB Pins GHA, GHB Pins GLA, GLB Pins CA, CB ESD Rating, Human Body Model ESD Rating, Charged Device Model Ambient Operating Temperature Range Continuous Junction Temperature Transient Junction Temperature Storage Temperature Range *With respect to ground TA TJ(max) TJt Tstg Overtemperature event not exceeding 10 s, lifetime duration not exceeding 10 hr, guaranteed by design characterization Symbol VBB VDD VI VO VVREG VCPX VRDEAD VSX VGHX VGLX VCX AEC Q100-002, all pins AEC Q100-011, all pins Range K Notes Rating -0.3 to 50 -0.3 to 7 -0.3 to 6.5 -0.3 to 6.5 -0.3 to 16 -0.3 to 16 -0.3 to 6.5 -5 to 55 VSX to VSX + 15 -5 to 16 -0.3 to VSX+15 2000 1000 -40 to 150 150 175 -55 to 150 Unit V V V V V V V V V V V V V C C C C Thermal Characteristics may require derating at maximum conditions, see application information Characteristic Package Thermal Resistance, Junction to Ambient Package Thermal Resistance, Junction to Pad Symbol RJA RJP Test Conditions* On 4-layer PCB based on JEDEC standard On 2-layer PCB with 3.8 in.2 of copper area each side Value 28 100 2 Unit C/W C/W C/W *Additional thermal information available on the Allegro website Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A4940 Automotive Full Bridge MOSFET Driver Functional Block Diagram Battery + CP VBB VDD CP2 CP1 Charge Pump Regulator Diagnostics & Protection Bootstrap Monitor CA GHA RGHA SA AHI ALO Low Side GND Bootstrap Monitor GLA RGLA RGLB RGHB VREG CREG VBAT FAULT CBOOTA High Side Control Logic BHI CB CBOOTB BLO High Side GHB SB RESET Low Side GND RDEAD AGND GND GLB Thermal Pad Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A4940 Automotive Full Bridge MOSFET Driver ELECTRICAL CHARACTERISTICS Valid at TJ = -40C to 150C, VBB = 7 to 50 V, VDD = 3 to 5.5 V; unless otherwise noted Characteristics Supply and Reference VBB Functional Operating Range1 VDD Range VBB Quiescent Current VDD Quiescent Current VBB VDD IBBQ IBBS IVDDQ IVDDS RESET = high, GHx, GLx = low, VBB = 12 V RESET= low, VBB = 12 V RESET = high, outputs low RESET = low VBB > 9 V, IREG = 0 to 8 mA 7.5 V < VBB 9 V, IREG = 0 to 6 mA VREG Output Voltage VREG 6 V < VBB 7.5 V, IREG = 0 to 5 mA 5.5 V < VBB 6 V, IREG < 4 mA Bootstrap Diode Forward Voltage Bootstrap Diode Resistance Bootstrap Diode Current Limit Gate Output Drive Turn-On Time Turn-Off Time Pull-up On Resistance Pull-down On Resistance GHx Output Voltage GLx Output Voltage Turn-Off Propagation Delay2 Turn-On Propagation Delay2 Propagation Delay Matching - Phase to Phase Propagation Delay Matching - On to Off tr tf RDS(on)UP RDS(on)DN VGH VGL tp(off) tp(on) tPP tOO Input change to unloaded gate output change Input change to unloaded gate output change Same phase change Single phase RDEAD tied to GND RDEAD = 3 k Dead Time2 tDEAD RDEAD = 30 k RDEAD = 240 k RDEAD tied to VDD CLOAD = 1 nF, 20% to 80% points CLOAD = 1 nF, 80% to 20% points TJ = 25C, IGHX = -150 mA TJ = 150C, IGHX = -150 mA TJ = 25C, IGLX = -150 mA TJ = 150C, IGLX = -150 mA Bootstrap capacitor fully charged - - 8 13 3 6 VCX - 0.2 VREG - 0.2 60 60 - - - - 815 - - 35 20 11 18.5 6 9 - - 90 90 10 10 0 180 960 3.5 6 - - 16 24 8 12 - - 150 150 - - - - 1150 - - ns ns V V ns ns ns ns ns ns ns s s VfBOOT rD IDBOOT ID = 10 mA ID = 100 mA rD(100mA) = (VfBOOT(150mA) - VfBOOT(50mA)) / 100 mA 5.5 3 - - - - 12.65 12.65 2 x VBB - 2.5 8.5 0.4 1.5 6 250 - - 1 - 2 - 13 13 - 9.5 0.7 2.2 10 500 50 5.5 2 10 4 10 13.9 13.9 - - 1.0 2.8 20 750 V V mA A mA A V V V V V V mA Symbol Test Conditions Min. Typ. Max. Unit Continued on the next page... Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A4940 Automotive Full Bridge MOSFET Driver ELECTRICAL CHARACTERISTICS (continued) Valid at TJ = -40C to 150C, VBB = 7 to 50 V, VDD = 3 to 5.5 V; unless otherwise noted Characteristics Logic Inputs and Outputs FAULT Output (Open drain) FAULT Output Leakage Current3 RDEAD Current3 Input Low Voltage Input High Voltage Input Hysteresis Input Current (Except RESET)3 Input Pull-down Resistor (RESET) RESET Pulse Time Protection VREG Undervoltage Lockout Bootstrap Undervoltage Bootstrap Undervoltage Hysteresis VDD Undervoltage Turn-Off VDD Undervoltage Hysteresis Overtemperature Flag Overtemperature Hysteresis 1Function Symbol VOL IOH IDEAD VIL VIH VIHYS IIN RPD tRES VREGUVON VBOOTUV VBOOTUVHYS VDDUV VDDUVHYS TJF TJFHYS VDD falling VREG rising 0 V < VIN < VDD Test Conditions IFAULTOL = 1 mA, fault present VFAULTO = 5 V, fault not present RDEAD = GND Min. - -1 -200 - 0.7 x VDD 300 -1 - 0.1 7.5 6.6 59 - 2.45 50 150 - Typ. - - - - - 500 - 50 Max. 0.4 1 -70 0.3 x VDD - - 1 - 3.5 Unit V A A V V mV A k s V V %VREG %VREG V mV C C 8 7.1 - 20 2.7 100 170 15 8.5 7.6 69 - 2.85 150 - - VREGUVOFF VREG falling VBOOT falling, VCX - VSX Temperature increasing Recovery = TJF - TJFHYS is correct, but parameters are not guaranteed below the general limit (7 V). 2See Gate Drive Timing. 3For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. Gate Drive Timing Diagrams xHI xLO tp(off) GHx GLx tDEAD tp(off) Complementary High side only tDEAD GHx GLx xHI xLO tp(on) tp(off) GHx GLx tp(on) tp(off) xHI xLO Low side only Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A4940 Automotive Full Bridge MOSFET Driver Functional Description The A4940 is a full-bridge MOSFET driver (pre-driver) requiring an unregulated supply of 7 to 50 V and a logic supply from 3 to 5.5 V. The four gate drives are capable of driving a wide range of N-channel power MOSFETs, and are configured as two highside drives and two low-side drives. The A4940 provides all the necessary circuits to ensure that the gate-source voltage of both high-side and low-side external MOSFETs are above 10 V, at supply voltages down to 7 V. For extreme battery voltage drop conditions, correct functional operation is guaranteed at supply voltages down to 5.5 V, but with a reduced gate drive voltage. The A4940 provides the interface between the logic level outputs of a microcontroller and the high current, high voltage gate drive for N-channel power MOSFETs in a full-bridge configuration. Typically, the power full-bridge will be used for brush DC motor control or other high current inductor loads. Each MOSFET in the bridge is controlled by an independent logic level input compatible with 3.3 or 5 V logic outputs. Cross-conduction (shootthrough) in the external bridge is avoided by an adjustable dead time. A low power sleep mode allows the A4940, the power bridge, and the load to remain connected to a vehicle battery supply without the need for an additional supply switch. The A4940 provides a single fault flag to indicate undervoltage and overtemperature conditions. Power Supplies Two power supply connections are required, one for the logic interface, and one for the analog and output drive sections. The logic supply, connected to VDD, allows the flexibility of a 3.3 or 5 V logic interface. The main power supply should be connected to VBB through a reverse voltage protection circuit. Both supplies should be decoupled with ceramic capacitors connected close to the supply and ground pins. The A4940 operates within specified parameters with a VBB supply from 7 to 50 V and will function correctly with a supply down to 5.5 V. This provides a very rugged solution for use in the harsh automotive environment. Gate Drives The A4940 is designed to drive external, low on-resistance, power N-channel MOSFETs. It supplies the large transient currents necessary to quickly charge and discharge the external MOSFET gate capacitance in order to reduce dissipation in the MOSFET during switching. The charge and discharge rate can be controlled using an external resistor in series with the connection to the gate of the MOSFET. Gate Drive Voltage Regulation The gate drives are powered by an internal regulator, which limits the supply to the drives and therefore the maximum gate voltage. When the VBB supply is greater than about 16 V, the regulator is a simple linear regulator. Below 16 V, the regulated supply is maintained by a charge pump boost converter, which requires a pump capacitor connected between the CP1 and CP2 pins. This capacitor must have a minimum value of 220 nF, and is typically 470 nF. The regulated voltage, 13 V typical, is available on the VREG pin. A sufficiently large storage capacitor must be connected to this pin to provide the transient charging current to the low-side drives and the bootstrap capacitors. GLA and GLB Pins These are the low-side gate drive outputs for the external N-channel MOSFETs. External resistors between the gate drive output and the gate connection to the MOSFET (as close as possible to the MOSFET) can be used to control the slew rate seen at the gate, thereby providing some control of the di/dt and dv/dt of the SA and SB outputs. GLx going high turns on the upper half of the drive, sourcing current to the gate of the lowside MOSFET in the external power bridge, turning it on. GLx going low turns on the lower half of the drive, sinking current from the external MOSFET gate circuit to GND pin, turning off the MOSFET. SA and SB Pins Directly connected to the motor, these terminals sense the voltages switched across the load. These terminals are also connected to the negative side of the bootstrap capacitors and are the negative supply connections for the floating high-side drives. The discharge current from the high-side MOSFET gate capacitance flows through these connections, which should have low impedance circuit connections to the MOSFET bridge. GHA and GHB Pins These terminals are the high-side gate drive outputs for the external N-channel MOSFETs. External resistors between the gate drive output and the gate connection to the MOSFET (as close as possible to the MOSFET) can be used to control the slew rate seen at the gate, thereby controlling the di/dt and dv/dt of the SA and SB outputs. GHx going high turns Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A4940 Automotive Full Bridge MOSFET Driver on the upper half of the drive, sourcing current to the gate of the high-side MOSFET in the external motor-driving bridge, turning it on. GHx going low turns on the lower half of the drive, sinking current from the external MOSFET gate circuit to the corresponding Sx pin, turning off the MOSFET. CA and CB Pins These are the high-side connections for the bootstrap capacitors and are the positive supply for the high-side gate drives. The bootstrap capacitors are charged to approximately VREG when the associated output Sx terminal is low. When the Sx output swings high, the charge on the bootstrap capacitor causes the voltage at the corresponding Cx terminal to rise with the output to provide the boosted gate voltage needed for the high-side MOSFETs. RDEAD Pin This pin controls internal generation of dead time during MOSFET switching. Cross-conduction is prevented by the gate drive circuits, which introduce a dead time, tDEAD, between switching one MOSFET off and the complementary MOSFET on. * When an external resistor greater than 3 k is connected between RDEAD and AGND, the dead time is derived from the resistor value. * When RDEAD is connected directly to VDD, tDEAD defaults to a value of 6 s typical. Logic Control Inputs Four low voltage-level digital inputs provide control for the gate drives. These logic inputs all have a typical hysteresis of 500 mV to improve noise performance. They provide individual direct control over each power MOSFET, subject to cross-conduction prevention, and can be used together to provide fast decay or slow decay with high-side or low-side recirculation. AHI, ALO, BHI and BLO Pins These directly control the gate drives. The xHI inputs control the high-side drives and the xLO Table 1. Input Logic Pin Setting RESET H H H H L xHI H L H L x xLO L H H L x GHx H L L L Z GLx L H H L Z Sx H L L Z Z inputs control the low-side drives. Internal lockout logic ensures that the high-side output drive and low-side output drive cannot be active simultaneously. Table 1 shows the logic truth table. RESET Pin This is an active-low input, and when active it allows the A4940 to enter sleep mode. When RESET is held low, the regulator and all internal circuitry are disabled and the A4940 enters sleep mode. Before fully entering sleep mode, there is a short delay while the regulator decoupling and storage capacitors discharge. This typically takes a few milliseconds, depending on the application conditions and component values. During sleep mode, current consumption from the VBB supply is reduced to a minimal level. In addition, latched faults and the corresponding fault flags are cleared. When the A4940 is coming out of sleep mode, the protection logic ensures that the gate drive outputs are off until the charge pump reaches its correct operating condition. The charge pump stabilizes in approximately 3 ms under nominal conditions. RESET can be used also to clear latched fault flags without entering sleep mode. To do so, hold RESET low for the reset pulse time, tRES . This clears the latched bootstrap capacitor undervoltage fault that disables the outputs. Note that the A4940 can be configured to start without any external logic input. To do so, pull up the RESET pin to VBB by means of an external resistor. The resistor value should be between 20 and 33 k. Diagnostics Several diagnostic features are integrated into the A4940 to provide indication of fault conditions. In addition to system wide faults such as undervoltage and overtemperature, the A4940 integrates individual bootstrap voltage monitors for each bootstrap capacitor. Mode of Operation High side MOSFET conducting Low Side MOSFET conducting Low Side MOSFET conducting - cross-conduction prevention High side and low side off All gate drives inactive, all MOSFETs off Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A4940 Automotive Full Bridge MOSFET Driver FAULT Pin This is an open drain output fault flag, which indicates a fault condition by its state, as shown in table 2. It must be pulled to VDD with an external resistor, typically 10 to 47 k. Fault States Overtemperature If the junction temperature exceeds the over-temperature threshold, 170C typical, the A4940 will enter the overtemperature fault state and FAULT will go low. The overtemperature fault state, and FAULT, will only be cleared when the temperature drops below the recovery level defined by TJF - TJFHYS. No circuitry will be disabled. External control circuits must take action to limit the power dissipation in some way so as to prevent overtemperature damage to the A4940 chip and unpredictable device operation. VREG Undervoltage VREG supplies the low-side gate driver and the bootstrap charge current. It is critical to ensure that the voltages are sufficiently high before enabling any of the outputs. If the voltage at VREG, VREG , drops below the falling VREG undervoltage lockout threshold, VREGUVOFF, then the A4940 will enter the VREG undervoltage fault state. In this fault state FAULT will be low, and the outputs will be disabled. The VREG undervoltage fault state and the fault flags will be cleared when VREG rises above the rising VREG undervoltage lockout threshold, VREGUVON. The VREG undervoltage monitor circuit is active during powerup, and the A4940 remains in the VREG undervoltage fault state until VREG is greater than the rising VREG undervoltage lockout threshold, VREGUVON. Bootstrap Capacitor Undervoltage The A4940 monitors the voltage across the individual bootstrap capacitors to ensure they have sufficient charge to supply the current pulse for the high- side drive. Before a high-side drive can be turned on, the voltage across the associated bootstrap capacitor must be higher than the turn-on voltage limit. If this is not the case, then the A4940 will start a bootstrap charge cycle by activating the complementary low-side drive. Under normal circumstances, this will charge the bootstrap capacitor above the turn-on voltage in a few microseconds and the high-side drive will then be enabled. The bootstrap voltage monitor remains active while the high-side drive is active and, if the voltage drops below the turn-off voltage, a charge cycle will be initiated. In either case, if there is a fault that prevents the bootstrap capacitor charging, then the charge cycle will timeout, FAULT will be low, and the outputs will be disabled. The bootstrap undervoltage fault state remains latched until RESET is set low. VDD Undervoltage The logic supply at VDD is monitored to ensure correct logical operation. If the voltage at VDD, VDD, drops below the falling VDD undervoltage lockout threshold, VDDUVOFF , then the A4940 will enter the VDD undervoltage fault state. In this fault state, FAULT will be low, and the outputs will be disabled. In addition, because the state of other reported faults cannot be guaranteed, all fault states are reset and replaced by a VDD undervoltage fault state. For example, a VDD undervoltage will reset an existing boostrap undervoltage fault condition and replace it with a VDD undervoltage fault. The VDD undervoltage fault state and the fault flag will be cleared when VDD rises above the rising VDD undervoltage lockout threshold defined by VDDUVOFF +VDDUVHYS. The VDD undervoltage monitor circuit is active during power-up, and the A4940 remains in the VDD undervoltage fault state until VDD is greater than the rising VDD undervoltage lockout threshold, VDDUVOFF +VDDUVHYS. Table 2. Fault Definitions FAULT Pin Setting High Low Low Low Low Fault Description No Fault Overtemperature VDD undervoltage VREG undervoltage Bootstrap undervoltage Disable Outputs* No No Yes Yes Yes Fault Latched - No No No Yes *Yes indicates all gate drives low, and all MOSFETs off. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A4940 Automotive Full Bridge MOSFET Driver Application Information Dead Time To prevent cross-conduction (shoot-through) in any phase of the power MOSFET bridge, it is necessary to have a dead time delay, tDEAD , between a high-side or low-side turn-off and the next complementary turn-on event. The potential for cross-conduction occurs when any complementary high-side and low-side pair of MOSFETs are switched at the same time; for example, when using synchronous rectification or after a bootstrap capacitor charging cycle. In the A4940, the dead time for both phases is set by a single dead-time resistor, RDEAD, between the RDEAD and AGND pins. For RDEAD between 3 and 240 k at 25C, the value of tDEAD (ns), can be approximated by: The maximum dead time of 6 s typical can be set by connecting the RDEAD pin directly to VDD. Alternatively, the dead time in the A4940 can be disabled by connecting the RDEAD pin directly to GND. In this case the required dead time must be supplied by the external controller. The choice of power MOSFET and external series gate resistance determine the selection of the dead-time resistor, RDEAD. The dead time should be long enough to ensure that one MOSFET in a phase has stopped conducting before the complementary MOSFET starts conducting. This should also take into account the tolerance and variation of the MOSFET gate capacitance, the series gate resistance, and the on-resistance of the A4940 internal drives. Dead time will be present only if the on-command for one MOSFET occurs within tDEAD after the off-command for its complementary MOSFET. In the case where one side of a phase drive is permanently off, for example when using diode rectification with slow decay, then the dead time will not occur. In this case the gate drive will turn on within the specified propagation delay after the corresponding phase input goes high. (Refer to the Gate Drive Timing diagrams.) Braking The A4940 can be used to perform dynamic braking by forcing all low-side MOSFETs on and all high-side MOSFETs off (ALO=BLO=1, AHI=BHI=0) or, conversely, by forcing all lowside off and all high-side on (ALO=BLO=0, AHI= BHI=1). This effectively short-circuits the back EMF of the motor, creating a breaking torque. During braking, the load current can be approximated by: IBRAKE Vbemf RL t DEAD 50 + 7200 1.2 + ( 200 / RDEAD ) where RDEAD is in k. Figure 1 illustrates the relationship of tDEAD and RDEAD , with the greatest accuracy obtained for values of RDEAD between 6 and 60 k. The IDEAD current can be estimated by: IDEAD 1.2 RDEAD 4.5 4.0 3.5 3.0 tDEAD (s) 2.5 2.0 1.5 1.0 0.5 0 0 50 100 150 200 250 RDEAD (k) 300 350 400 where Vbemf is the voltage generated by the motor and RL is the resistance of the phase winding. Care must be taken during braking to ensure that maximum ratings of the power MOSFETs are not exceeded. Dynamic braking is equivalent to slow decay with synchronous rectification. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com Figure 1. Dead time versus values of RDEAD (full range). 9 A4940 Automotive Full Bridge MOSFET Driver during the charge transfer, which should be 400 mV or less. The capacitor is charged whenever the Sx pin is pulled low and current flows from VREG through the internal bootstrap diode circuit to CBOOT. Bootstrap Charge Management The A4940 provides automatic bootstrap capacitor charge management. The bootstrap capacitor voltage for each phase is continuously checked to ensure that it is above the bootstrap under-voltage threshold, VBOOTUV. If the bootstrap capacitor voltage drops below this threshold, when the corresponding high-side is active, the A4940 will turn on the necessary low-side MOSFET, and continue charging until the bootstrap capacitor exceeds the undervoltage threshold plus the hysteresis, VBOOTUV + VBOOTUVHYS . If the bootstrap capacitor voltage is below the threshold, when the corresponding high-side is commanded to turn on, the A4940 will not attempt to turn on the high-side MOSFET, but will turn on the necessary low-side MOSFET to charge the bootstrap capacitor until it exceeds the undervoltage threshold plus the hysteresis. The minimum charge time is typically 7 s, but may be longer for very large values of bootstrap capacitor (>1000 nF). If the bootstrap capacitor voltage does not reach the threshold within approximately 200 s, an undervoltage fault will be flagged. VREG Capacitor Selection The internal reference, VREG , supplies current for the low-side gate drive circuits and the charging current for the bootstrap capacitors. When a low-side MOSFET is turned on, the gatedrive circuit will provide the high transient current to the gate that is necessary to turn on the MOSFET quickly. This current, which can be several hundred milliamperes, cannot be provided directly by the limited output of the VREG regulator, and must be supplied by an external capacitor connected to the VREG pin. The turn-on current for the high-side MOSFET is similar in value to that for the low-side MOSFET, but is mainly supplied by the bootstrap capacitor. However the bootstrap capacitor must then be recharged from the VREG regulator output. Unfortunately the bootstrap recharge can occur a very short time after the low-side turn-on occurs. This requires that the value of the capacitor connected between VREG and AGND should be high enough to minimize the transient voltage drop on VREG for the combination of a low-side MOSFET turn-on and a bootstrap capacitor recharge. A value of 20 x CBOOT is a reasonable value. The maximum working voltage will never exceed VREG, so the capacitor can be rated as low as 15 V. This capacitor should be placed as close as possible to the VREG pin. Bootstrap Capacitor Selection The bootstrap capacitors, CBOOTx, must be correctly selected to ensure proper operation of the A4940. If the capacitances are too high, time will be wasted charging the capacitor, resulting in a limit on the maximum duty cycle and the PWM frequency. If the capacitances are too low, there can be a large voltage drop at the time the charge is transferred from CBOOTx to the MOSFET gate, due to charge sharing. To keep this voltage drop small, the charge in the bootstrap capacitor, QBOOT, should be much larger than the charge required by the gate of the MOSFET, QGATE. A factor of 20 is a reasonable value, and the following formula can be used to calculate the value for CBOOT: QBOOT = CBOOT = QGATE CBOOT = QGATE VBOOT VBOOT 20 20 where VBOOT is the voltage across the bootstrap capacitor. The voltage drop across the bootstrap capacitor as the MOSFET is being turned on, V, can be approximated by: V QGATE CBOOT So for a factor of 20, V would be approximately 5% of VBOOT . The maximum voltage across the bootstrap capacitor under normal operating conditions is VREG(max). In most applications, with a good ceramic capacitor the working voltage can be limited to 16 V. Bootstrap Charging It is good practice to ensure the high side bootstrap capacitor is completely charged before a high side PWM cycle is requested. The time required to charge the capacitor, tCHARGE (s), is approximated by: tCHARGE CBOOT V 100 where CBOOT is the value of the bootstrap capacitor, in nF, and V is the required voltage of the bootstrap capacitor. At power-up and when the drives have been disabled for a long time, the bootstrap capacitor can be completely discharged. In this case V can be considered to be the full high-side drive voltage, 12 V. Otherwise, V is the amount of voltage dropped Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 A4940 Automotive Full Bridge MOSFET Driver are recommendations regarding some of these considerations: * The A4940 ground, GND, and the high-current return of the external MOSFETs should return separately to the negative side of the motor supply filtering capacitor. This minimizes the effect of switching noise on the device logic and analog reference. * The exposed thermal pad should be connected to the GND pin and may form part of the Controller Supply ground (see figure 2). * Minimize stray inductance by using short, wide copper traces at the drain and source terminals of all power MOSFETs. This includes motor lead connections, the input power bus, and the common source of the low-side power MOSFETs. This will minimize voltages induced by fast switching of large load currents. * Consider the use of small (100 nF) ceramic decoupling capacitors across the sources and drains of the power MOSFETs to limit fast transient voltage spikes caused by the inductance of the circuit trace. * The ground connection to RDEAD should be connected independently directly to the AGND pin. This sensitive component should never be connected directly to the supply common or to a common ground plane. It must be referenced directly to the AGND pin. * Supply decoupling for VBB, VREG, and VDD should be connected to the Controller Supply ground which is independently connected close to the GND pin. The decoupling capacitors should also be connected as close as possible to the relevant supply pin. Note that the above are only recommendations. Each application is different and may encounter different sensitivities. A driver running a few amps will be less susceptible than one running with 150 A and each design should be tested at the maximum current to ensure any parasitic effects are eliminated. Supply Decoupling Because this is a switching circuit, there are current spikes from all supplies at the switching points. As with all such circuits, the power supply connections should be decoupled with a ceramic capacitor, typically 100 nF, between the supply pin and ground. These capacitors should be connected as close as possible to the device supply pins, VDD and VBB, and the ground pin, GND. Power Dissipation In applications where a high ambient temperature is expected the on-chip power dissipation may become a critical factor. Careful attention should be paid to ensure the operating conditions allow the A4940 to remain in a safe range of junction temperature. The power consumed by the A4940, PD, can be estimated by : PD = PBIAS +PCPUMP + PSWITCHING given PBIAS = VBB x IBB PCPUMP = [(2 x VBB) - VREG) x Iav PCPUMP = (VBB - VREG) x Iav Iav = QGATE x VREG x N x fPWM PSWITCHING = QGATE x VREG x N x fPWM x Ratio Ratio = 10 / (RGATE + 10) where N is the quantity of MOSFETs switching during a PWM cycle. N = 1 for slow decay with diode recirculation, N = 2 for slow decay with synchronous rectification or fast decay with diode recirculation, and N = 4 for fast decay with synchronous rectification. Layout Recommendations Careful consideration must be given to PCB layout when designing high frequency, fast switching, high current circuits. The following for VBB < 15 V for VBB > 15 V Optional reverse battery protection VBB GHB VREG GHA A4940 VDD SA SB RDEAD RDEAD GLA GLB + Supply Motor AGND GND Power Ground Supply Common Controller Supply Ground Figure 2. Supply routing suggestions Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 A4940 Automotive Full Bridge MOSFET Driver Input and Output Structures CP1 Cx 20V 18V GHx 19V 18V 18V Sx VREG 18V 18V 18V 18V 6V ESD CP2 VREG VBB VDD (B) Supply protection structures ESD 18V 1 k FAULT RESET GLx 10 k GND 50 8.5V 6V 6V 50 k (A) Gate drive outputs ESD (C) FAULT outputs ESD 1.2V (D) RESET input AHI ALO BHI BLO 3 k RDEAD 100 8.5V 8.5V (E) Logic inputs: no pull-down resistor (F) RDEAD Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12 A4940 Automotive Full Bridge MOSFET Driver Pin-out Diagram RESET 1 GND 2 GLB 3 SB 4 GHB 5 CB 6 VREG 7 CA 8 GHA 9 SA 10 GLA 11 VBB 12 PAD 24 FAULT 23 RDEAD 22 AGND 21 VDD 20 AHI 19 ALO 18 BHI 17 BLO 16 GND 15 GND 14 CP1 13 CP2 Terminal List Number AGND AHI ALO BHI BLO CA CB CP1 CP2 FAULT GHA GHB GLA GLB GND PAD RDEAD RESET SA SB VBB VDD VREG Name 22 20 19 18 17 8 6 14 13 24 9 5 11 3 2,15,16 - 23 1 10 4 12 21 7 Ground Reference Control Input A High Side Control Input A Low Side Control Input B High Side Control Input B Low Side Bootstrap Capacitor A Bootstrap Capacitor B Pump Capacitor Pump Capacitor Fault Output High-side Gate Drive A High-side Gate Drive B Low-side Gate Drive A Low-side Gate Drive B Ground Exposed pad for thermal dissipation, connect to GND Dead time setting input Reset Input Load Connection A Load Connection B Main Supply Logic Supply Regulated 13 V Function Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 13 A4940 Automotive Full Bridge MOSFET Driver Package LP 24-Pin TSSOP with Exposed Thermal Pad 7.800.10 24 8 0 0.20 0.09 0.45 0.65 B 3 NOM A 4.400.10 6.400.20 0.60 0.15 1.00 REF 3.00 6.10 1 2 4.32 NOM C 0.25 BSC SEATING PLANE SEATING PLANE GAUGE PLANE 1.65 C 4.32 PCB Layout Reference View 24X 0.10 C 0.30 0.19 0.65 BSC 0.15 0.00 1.20 MAX For Reference Only; not for tooling use (reference MO-153 ADT) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (bottom surface); dimensions may vary with device C Reference land pattern layout (reference IPC7351 TSOP65P640X120-25M); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) Copyright (c)2009, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro's products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 14 |
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